1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device capable of operating refresh operations according to temperature.
2. Description of the Related Art
Generally, a semiconductor memory device such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) includes a plurality of memory banks for storing data, and each of the plurality of memory banks has more than en-million memory cells, Each of the memory cells comprises a cell capacitor and a cell transistor, and the semiconductor memory device stores data by charging and discharging the cell capacitor.
Ideally, the amount of charge stored in the cell capacitor is supposed to remain the same. However, in reality, the amount of charge stored in the cell capacitor changes due to a voltage difference between the peripheral circuits. That is, there may be outflow of charge from the charged cell capacitor, or there may be inflow of charge when the cell capacitor is discharged. A change in the amount of charge correlates to a change in the data stored in the cell capacitor, and therefore a loss of charge may result in a loss of data. Semiconductor memory devices perform refresh operations to prevent a loss of data due to unintended changes in cell capacitor charges.
FIG. 1 is a block diagram illustrating an existing semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes an oscillating signal generation section 110, a refresh signal generation section 120, a word line control section 130, and a memory cell array 140.
The oscillating signal generation section 110 generates an oscillation signal OSC with a predetermined period, in response to a refresh command signal CMD_REF. The refresh signal generation section 120 receives the oscillation signal OSC and generates a refresh signal INN_REF, which is enabled with the predetermined period of the oscillation signal OSC. The word line control section 130 controls enablement of a plurality of word lines through word line signals WL in response to the refresh signal INN_REF. The memory cell array 140 performs the refresh operation in response to the word line signals WL.
Semiconductor memory device deteriorate based on how long they are in service and how much use it has received. That is, semiconductor memory devices degrade as they are written, read from, and they also degrade simply due to the passage of time Eventually they get to the point where they need to be discarded. As the semiconductor memory device deteriorates, refresh operations are likely to malfunction. The malfunction of refresh operations may be the direct cause of reduced reliability of stored data. Therefore, it is necessary to adapt the refresh operations to the possibly deteriorated condition of the semiconductor memory device.